1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a method of fabricating a capacitor structure for a dynamic random access memory (DRAM).
2. Description of the Related Art
A DRAM is a widely used integrated circuit device, and it plays an indispensable role in the electronic industry. FIG. 1 is a circuit diagram illustrating a conventional DRAM memory cell. As shown in FIG. 1, a memory cell includes a transfer transistor T and a storage capacitor C. The source electrode of the transfer transistor T is coupled to a corresponding bit line BL. The drain electrode of the transfer transistor T is coupled to a storage electrode 6 of the storage capacitor C. The gate electrode of the transfer transistor T is coupled to a corresponding word line WL. An opposed electrode 8 of the storage capacitor C is coupled to a stationary voltage source V.sub.CP. A dielectric layer 7 is deposited between the storage electrode 6 and the opposed electrode 8. As known by those skilled in this art, the storage capacitor C is used for storing data, and should have enough capacitance to avoid a loss of data.
In a conventional fabricating process for a DRAM device having a storage capacity below 1 MB, a two dimensional capacitance device, e.g., a planar-type capacitor, is widely used for storing data. As shown in FIG. 2, a field oxide layer 11 is formed on a substrate 10 to define an active region, then gate oxide layer 12, gate electrode layer 13, and source and drain electrode areas 14 are formed in sequence to form a transfer transistor T. On the surface of the substrate 10, a dielectric layer 7 and a conductive layer 8 are formed on one side adjacent to the drain. The area where the dielectric layer 7 and the conductive layer 8 join with the substrate 10 forms a storage capacitor C. However, the planar-type capacitor occupies a relatively large surface area of the device to form the storage capacitor C, which is at odds with the desire for large scale integration of the DRAM device.
A highly integrated DRAM, e.g., with a storage capacity of 4 MB or above, needs to use a three dimensional capacitance structure, such as a stack-type capacitor or a trench type capacitor, in order to realize a structure with reduced surface area requirements.
FIG. 3 is a cross-sectional diagram illustrating the structure of a conventional stack-type capacitor. On a substrate 10, a field oxide layer 11, a gate oxide layer 12, a gate electrode layer 13, and source-drain electrode areas 14 are formed in sequence to construct a transfer transistor T. Next, an insulating layer 15 is formed and a contact opening is formed by etching the source-drain electrode areas 14. Then, a first polysilicon layer 6, which is used as a storage electrode, a dielectric layer 7 and a second polysilicon layer 8, which is used as an opposed electrode, are formed in sequence on the device. In this way, a DRAM memory cell with stack-type capacitor C is completed. A memory cell should offer enough capacitance to assure the operational quality of the device as the size of the device is diminished. However, when a memory cell is even more highly integrated, such as when fabricating a DRAM with a storage capacity of 64 MB or above, the above mentioned structure of a stack-type capacitor is no longer adequate.
FIG. 4 is a cross-sectional diagram illustrating a structure of conventional trench-type capacitor C. First, a transfer transistor T is formed on a substrate 10 by ordinary processing, including a gate oxide layer 12, a gate electrode layer 13, and source-drain electrode areas 14. On the surface of the substrate 10, a deep trench is etched on the side adjacent to the drain electrode 14. Next, a storage capacitor C is formed within the deep trench. The storage capacitor C includes a dielectric layer 7, an opposed electrode polysilicon layer 8 and a storage electrode 6 which is formed by the sidewalls of the substrate 10. However, to raise the capacitance, the structure and the fabricating method of this kind of capacitor may increase the surface area of electrode. Further, during the forming of the deep trench by etching, lattice defects will be generated on the substrate that increase current leakage and influence the characteristics of devices. Also, as the aspect ratio is increased, the etching rate will be decreased which adds to the difficulty of processing and adversely affects the efficiency of production.